This invention relates generally to level shifters that are utilized for example in shifting voltage levels in memories such as flash memories.
Flash memories may need a plurality of different voltage levels to perform read, programming and erase functions. Generally these voltages are produced by on chip charge pumps. A charge pump is a DC-to-DC voltage converter. The charge pump generates a desired voltage level by selectively clocking capacitors and transistors in a prescribed sequence.
Charge pumps may include a number of different stages. The amount of input current to the charge pump is generally proportional to the number of those stages. The voltages generated by the charge pump are eventually coupled to the gate, drain and source terminals of flash memory cells in a flash memory array by way of decoder and switch circuits. The decoder and switch circuits may be constructed using complementary metal oxide semiconductor (CMOS) transistors. As a result, they may have a predetermined amount of associated capacitance.
The capacitance of the decoder and switch circuits may be significant. As a result, it may be necessary to keep the decoder and switch circuits in a ready state for memory read operations to achieve fast read access times. Thus, this capacitance is normally charged to prescribed read voltage levels during read mode. The read mode may include sequences when memory reads occur and intervening time periods between memory operations. During the intervening periods, the chip may assume a low power or standby state. Thus, this charging of capacitance, even in the low power or standby state may result in substantial leakage.
Subthreshold leakage occurs in these decoder and switch circuits. The leakage is significant because the decoder and switch capacitance must be fully charged even during standby. The leakage results in input current and therefore adds to the average current consumed during standby.
The widespread use of portable systems with on-board flash memories increases the need to limit power consumption. Even relatively small amounts of standby power consumption in devices with a large number of transistors may result in considerable drain in battery powered systems. Limited battery life means that reducing overall power consumption is a critical design goal.
Leakage power consumption occurs in the absence of a switching event. Leakage power consumption may be due to non-zero reverse bias leakage and subthreshold current. With a large number of transistors, leakage power consumption can significantly contribute to overall power consumption. Subthreshold leakage is due to carrier diffusion between the source and drain regions of transistors in weak inversion. An MOS transistor in the subthreshold operating region may behave like a bipolar device, exhibiting exponential dependence on the gate-to-source voltage. Particularly when the gate-to-source voltage is smaller than, but very close to, the threshold voltage of the device, subthreshold leakage current may become significant.
Level shifters may be used in connection with the decoder and switch circuits. Steering logic may be utilized to select the appropriate voltage for a given memory function such as read, program or erase. Level shifters may experience significant standby power consumption.
Thus, there is a need to reduce level shifter standby power consumption.